FPGA-Based Real-Time Auction System

Project Overview

This project is a real-time auction system built by combining an FPGA board’s I/O devices with combinational and sequential logic. It accepts bids from a keypad, compares each bid with the current price, and updates the display only when the new amount is higher. The auction closes after eight seconds without a valid bid or immediately when the maximum value of 99,999,999 is entered.

The system was developed by a two-person team for Pusan National University’s Logic Circuit Design and Laboratory course in 2023. We designed the individual logic modules as block diagrams in Quartus Prime, connected them through the top-level Auction_System circuit, and verified their behavior on a Cyclone V FPGA board.

Demonstration Video

Auction Flow

Press * → Enter bid → Confirm with # → Compare prices → Update or reject → Close auction

1. Pressing * starts the auction or prepares the system for a new bid. The opening price is zero, and all eight countdown LEDs turn on.
2. The bidder enters an amount of up to eight digits on the keypad and confirms it with #.
3. A bid higher than the current price is stored and shown on the 7-segment display, while the countdown resets to eight seconds.
4. A bid less than or equal to the current price is rejected without resetting the active timer.
5. If eight seconds pass without a valid bid, or if 99,999,999 is entered, the current price becomes the final winning bid.

The full-color LED is green while the auction is active and red after it closes. Eight additional LEDs visualize the remaining time by switching off one per second.

Logic Design

• Input conversion and edge handling: d2b converts the 0–9 keypad signals into 4-bit values, while trigger prevents a single key press from being stored multiple times.
• Eight-digit storage: Eight 4-bit registers in new_8_sram shift in the entered digits, and curr_8_sram retains the accepted highest bid.
• Bid comparison: EightDigitComparator combines eight 4-bit comparisons from the most significant digit downward. It emits the Gt_B update signal only when # is pressed and the new bid is greater.
• 7-segment output: counter8 cycles through the eight display positions, while multiplexers and the b2seg decoder dynamically present the current bid.
• Eight-second timer: Six CNT10 stages divide the 1 MHz reference clock into a one-second pulse. An eight-step counter drives the remaining-time LEDs and restarts after every accepted bid.

My Contributions

According to the project report’s task allocation, I was responsible for the core input, comparison, display, and timing circuits.

• Designed the keypad bid-entry circuit
• Built the current-price update logic using eight-digit comparison and register modules
• Designed the multiplexed eight-digit 7-segment display circuit
• Implemented the one-second pulse generator and eight-second countdown timer
• Integrated the modules and verified their I/O behavior on the FPGA board

Results

The final circuit passed the Quartus Prime Fitter for the Cyclone V device using 79 ALMs, 112 registers, and 46 pins. The completed system covered the core auction flow: bid entry and comparison, current-price and timer updates after valid bids, multiplexed price display, and auction termination on timeout or the maximum bid.

Additional piezo alerts for the remaining time and rejected bids were removed from the final scope because of output constraints and circuit complexity. Auction progress and remaining time were instead communicated through the full-color status LED and the eight countdown LEDs.

Tech Stack

FPGA · Cyclone V · Quartus Prime 20.1 · Block Diagram/Schematic · Verilog HDL · Combinational & Sequential Logic · Keypad · 7-Segment Display · Full Color LED